The present invention relates to test fixtures for use in testing printed circuit boards, and in particular, test fixtures which include electrostatic discharge (ESD) protection.
Automatic test equipment for checking printed circuit boards (PCBs) has long been well known. For the sake of consistency and convenience, the printed circuit board and the circuitry thereon to be checked, such as components and lead lines therebetween, will be referred to hereafter as a xe2x80x9cunit under testxe2x80x9d, or xe2x80x9cUUT.xe2x80x9d A standard and well known test approach utilizes a xe2x80x9cbed of nailsxe2x80x9d test fixture in which a great number of arrayed, nail-like test probes are provided, each having a tip arranged to make electrical contact with a designated test point of the UUT.
Any particular circuit laid out on a printed circuit board is likely to be different from all other circuits. Consequently, a xe2x80x9cbed of nailsxe2x80x9d arrangement for contacting test points in a particular circuit must be customized for each circuit. When the circuit to be tested is designed, a pattern of test points to be used in checking the circuit is selected, and a corresponding array of test probes are configured in a test fixture. A typical test fixture may have five hundred (500) test probes, and possibly up to two thousand (2000) or more test probes.
It is commonly known that electrostatic discharge (ESD) can cause serious damage to semiconductor devices. Damage can occur by way of junction burnout when a localized voltage is induced by an electrostatic potential. If a sufficient current flows due to the induced electrostatic potential, thermal secondary breakdown can occur, thereby destroying the junction.
Another type of damage is dielectric breakdown which occurs when the induced potentials are of a magnitude high enough to xe2x80x9cpunch throughxe2x80x9d the insulating layer of silicon dioxide which protects the gate of Field Effect Transistors (FETs) and Metal-Oxide Silicon (MOS) type semiconductors.
Furthermore, metallization melt is another type of damage due to electrostatic discharge. Bond wires or metallization strips within the semiconductor burn out, like a fuse, when high currents induced by the electrostatic potential occur.
Various sources for developing an electrostatic potential exist in the work place. For example, electrostatic charge can accumulate due to the well known triboelectric effect generated during the normal act of walking across, for example, the surface of a rug. For example, a worker accumulates a charge which creates a field between himself and nearby grounded objects. Then, any objects placed in that field will have a voltage induced on them depending on their size and orientation. Such a voltage can easily exceed five thousand (5000) volts. Likewise, if a worker with such an accumulated static charge on him touches an electronic component, currents will flow through the semiconductor of the component and eventually to ground. The resultant voltage can cause dielectric breakdown or melt metallization.
It is well known that circuits are exposed to potentially damaging electrostatic charges in the course of being checked on automatic test equipment of the type such as briefly described above. An electrostatic charge can be built up on the printed circuit board as it is being moved from one location to another due to, for example, the triboelectric effect discussed above which occurs as the person carrying it walks along. Also, when vacuum is used to exert a force on the UUT to engage it against the bed of nails, air rushes through vents in the test fixture during the application of vacuum as well as the release of a vacuum. The friction of air particles moving against fixture surfaces is a source of electrostatic charge build-up. Furthermore, various fixture seals undergo a certain degree of motion as the vacuum is applied and the UUT is brought into engagement with the xe2x80x9cbed of nailsxe2x80x9d. This motion is a further source of electrostatic charge build-up.
Electrostatic voltages generated by the above-described causes can reach as high as one thousand (1000) volts from the top plate and up to five thousand (5000) volts inside the vacuum well of the fixture. Such electrostatic potentials far exceed the static susceptibility range of MOSFET chips (100 to 200 volts) as well as ECL bipolar devices (up to 500 volts).
A further concern besides rendering the semiconductor components inoperative is the electrostatic overstress effect. It can be caused even by an electrostatic charge which is only 25% of the static susceptibility values mentioned just above. This effect is such that the components seem to have survived the static without damage. However, it can cause parametric degradation, as well as cause the component to fail well before its specified mean time between failures. As integrated circuits are made with ever finer lines and ever thinner oxide layers, the danger of static will further aggravate the electrostatic overstress effect.
In order to protect the UUT from being damaged during the testing operation, it is desirable to accomplish several aims. Since it is not unlikely that an electrostatic charge will somehow accumulate on the test fixture, it is desirable to dissipate that charge relatively quickly, but not instantaneously such as undesirably occurs in an electrostatic discharge to ground with its attendant damaging effects. It is also desirable to prevent the test fixture itself from generating an electrostatic charge during operation of the automatic test equipment. In addition, if an undissipated electrostatic charge remains on the test fixture, it is desirable to prevent a spark from passing from the UUT to the test fixture when, for example, the operator brings the UUT towards the test fixture for mounting thereon.
Various approaches have been developed in an attempt to effectively deal with the electrostatic charges developed on a test fixture due to a variety of causes including those mentioned above. One approach is to ground the operator, such as by a wrist strap connected to ground. Although this eliminates the build-up of electrostatic charges due to the effect of the worker, it completely fails to deal with the other causes listed above.
Another approach utilizes an ionizer to blow ionized air across the fixture. However, its effect has been found to be limited because of the inability to access areas beneath the UUT where static charge is actually generated.
In yet another approach, an antistatic spray is applied to the fixture. However, this requires disassembly of the fixture which is a somewhat laborious operation. Also, the spray has to be reapplied relatively frequently, such as at one week intervals because it rubs off easily, evaporates (i.e. sublimes) or its electrical characteristics degrade. Also, such sprays are humidity dependent in their ability to prevent static buildup.
More recently, as described in U.S. Pat. No. 4,814,698 to St. Onge, et al., an anti-static coating 68 having a certain critical resistivity has been applied to areas of a test fixture 10 to reduce ESD (See FIG. 3). However, the test fixture 10 described by St. Onge is clearly for use with devices operating at relatively low frequencies. At frequencies between 1 Gigahertz (Ghz) and 60 Ghz, the anti-static coating 68 forms a shunt (i.e., short circuit) to ground for all active high frequency signals. This occurs because the impedance of the high speed (frequency) circuits greatly exceeds the static dissipative range for the coating 68. For example, the coating 68 has a resistivity in a range from 105-1010 ohms/sq. (See Abstract). Thus, at a frequency such as 500 MHZ, the coating will operate properly as a static dissipative layer. However, at higher frequencies (such as 1 GHz and above), the resistivity of the coating 68 will decrease, and the coating will act as a short circuit to ground.
Additionally, as described in U.S. Pat. No. 5,663,655 to Johnston et al., test fixtures which include ESD protection layers are known. Johnston shows a universal grid tester 10 which includes a grounding layer 26 to protect the device under test from ESD. The grounding layer 26 connects to spring-loaded plunger pins 22 of the tester 10 through a ground plane contact section 24 (See FIG. 3). However, the tester 10 described by Johnston includes many elements for transferring test signals to printed circuit board (PCB) under test 36. In particular, test signals are supplied to the PCB from switch cards 46, 48 to terminal pins 30, through barrel 24, through spring 54, and through pin 22 to receptacle 20 which contacts the PCB. This multitude of connections between the signal source and the PCB will cause each pin to receive slightly different signals due to the slight differences in DC resistance of the members (barrel 24, spring 54, etc.), especially with high frequency test signals (1 GHz and above). Additionally, as the frequency of the test signals increases, small variations in the DC resistance of the members will cause large swings in the AC test signals provided to the PCB.
Therefore, there is currently a need for a circuit test fixture which operates effectively at high frequencies.
The present invention is a device including a probe plate including a plurality of test pins, a conductive layer disposed in proximity to the probe plate and including a plurality of openings therein corresponding the plurality of test pins and, an insulator layer disposed on the conductive layer and including a plurality of openings therein corresponding the plurality of test pins.
The above and other advantages and features of the present invention will be better understood from the following detailed description of the preferred embodiments of the invention which is provided in connection with the accompanying drawings.